Protecting device for a semiconductor memory apparatus

ABSTRACT

A protecting device for a semiconductor memory which protects the plural semiconductor memory elements from damage due to an abnormal pulse being received from the driving circuits. The output signals from the precharge and chip select signal drivers in a MOS-RAM are sampled and time-delayed. The sampled signals are compared with the time delayed signals in gating circuits. If the sampled signals exceed a predetermined pulse width, sensing means are actuated to activate the alarm and terminate the source voltage to prevent damage to the memory elements.

United States Patent [1 1 Kodama July 22, 1975 4] PROTECTING DEVICE FORA 3,293,606 12/1966 Ackerman et a1. 307/234 SEMICONDUCTOR MEMORYAPPARATUS $458,822 7/1969 e s) K Kod T k J 3,652,943 3/1972 Picclnlli eta1 307/234 [75] Inventor. 0J1 ama, 0 yo, apan OTHER PUBLICATIONS [73]Asslgnee: Tokyo Sh'baura Electnc Company Pulse, Digital, and SwitchingWaveforms, Millman &

Ltd-9 Japan Taub, McGraw-Hill Book Co, p. 333, Fig. 9-27, [22] Filed:Apr. 20, 1973 Primary Examiner-J. D. Miller [21] Appl' 353,130 AssistantExaminer-Patrick R. Salce Attorney, Agent, or Firm-0b1on, Fisher,Spivak, [30] Foreign Application Priority Data Mcclelland & Maier 2 l 4-4 9 Apr 2. 972 Japan 7 074 [57] ABSTRACT 52 US. Cl. 317/33 R; 317/36TD; 307/234; A protecting device for a semiconductor memory 32 11 whichprotects the plural semiconductor memory ele- [51] Int. Cl. H02h 7/20mems from damage due to an abnormal Pulse being [58] Fi f Search H 37/33 R, 36 D, 33 S received from the driving circuits. The Outputsignals 307/233, 234, 202, 225, 226; 328/120, 1 10, from the prechargeand chip select signal drivers in a 111, 133, 112; 329/106; 323/119MOS-RAM are sampled and timede1ayed. The sampled signals are comparedwith the time delayed sig- 5 1 References Cied nals in gating circuits.1f the sampled signals exceed a UNITED STATES PATENTS predeterminedpulse width, sensing means are actuated to activate the alarm andterminate the source 3 3:; 307/234 voltage to prevent damage to thememory elements. 3,184,606 5/l965 Ovenden et al 307/234 3 Claims, 6Drawing Figures PATENTEDJUL22 ms 8 341 SHEET 1 A0 A] A2 A; A1; II T Y TT T 15 I3 MEMORY COLUMN MEMORY PORTION DECODER PORT/0N REFRESH REFRESHAMP AMR MEMORY COLUMN MEMORY 12- PORTION h-- DECODER PORTION M 34 ourPurROW Row H Z ,s DECODER DECODER FIG. 2

I PROTECTING DEVICE FOR A SEMICONDUCTOR MEMORY APPARATUS BACKGROUND OFTHE INVENTION I. Field of the Invention:

This invention relates to semiconductor memory apparatus, and moreparticularly to data storage apparatus for an electronic digitalcomputer which includes means for protecting the memory elements againstabnormal pulse signals occurring in the driving circuitry.

2. Description of the Prior Art:

An MOS (metal oxide semiconductor) random access memory(hereinaftercalled RAM)finds wide use as a data storage device in an electronicdigital computer. Generally, MOS-RAMs are classified into two types:static and dynamic. As seen in FIG. 1(a), the memory elements of astatic type of MOS-RAM are flip-flop circuits that comprise a feedbackcircuit using MOS transistors. In this device, storage information willnot be destroyed during the period that the source voltages V aresupplied to the memory elements. A dynamic type of device is shown inFIG. 1(b) as comprising MOS transistors with information being stored in:1 capacitor C. Stored information is maintained by refreshing thecharge on the capacitor, as is well-known in the art.

In FIG. 2, a representative dynamic type of MOS- RAM is shown, thecapacity of which is 1024 words X I bit. In the one chip shown, fourmemory portions 11, l2, l3 and 14 are arranged symmetrically in twoportions. Each memory portion comprises 256 bits (16 columns X 16 rows).The column decoders 15a and 15b and the row decoders 16a and 16b areprovided for memory portions l1, 12, I3 and 14, and said columns androws are selected by five bit addresses. A pair of refresh amplifiers l7and 18 are provided, one for memory portions 11 and I2 and one formemory portions 13 and 14 in the row direction as shown. One column inthe memory portions ll, 12, I3 and I4 is selected by a five bit addressby the column decoders 15a and 15b, and then the information is readfrom all of the thirty-two memory elements existing in said column. Therefresh amplifier 17 or 18 will then amplify the information in saidthirty-two memory elements. Thus, the information will be rewritten inthe memory elements of the selected column, and will then besimultaneously transmitted to the row decoders 16a and 161). These rowdecoders I6 and 16b select the information from one of the thirty-twoelements by a five bit address for transmission as the desired output.Since the thirty-two memory elements of one column are refreshed in oneread cycle, thirty-two read cycles are necessary to refresh the I024memory elements of all addresses.

FIG. 3 shows various waveforms illustrative of signals utilized in theMOS-RAM of FIG. 2. Waveform(a)of FIG. 3 represents the address settingperiod; waveform (b) represents the precharge signal (PRE); waveform (c)represents the chip select signal (CS) accumulated by said prechargesignal (PRE); waveform (d) represents the read write signal (R/W) andwaveforms (e) and (f) represent the input signal and output signal,respectively. Thus, it is seen that the most electric power is utilizedduring the time required to supply the PRE signal to each RAM device.Accordingly, if an abnormally large PRE signal occurred, it could causeserious damage to the semiconductor memory elements which receive PREsignals from driving circuits. Steps should be taken to avoid suchdamage by detecting such abnormal signals prior to their entry to thememory elements and by, for example, actuating an alarm and cut ting offthe source voltage when an abnormal signal is detected.

SUMMARY OF THE INVENTION It is therefore a primary object of the presentinvention to provide a new improved and unique semiconductor memoryapparatus which includes means for protecting the memory elementsagainst damage by ab normal driving circuitry signals, thus greatlyincreasing the reliability of an electronic digital computer.

The foregoing and other objects are attained in accordance with oneaspect of the present invention through the provision of a pair ofdetecting circuits for sampling the outputs of the precharge and chipselect signal drivers. The output from each detecting circuit is fed toa pair of serially-connected wave adjusting circuits which act on thesampled signal to compare it to a time-delayed version thereof. If theoutput pulse signal of either the precharge or chip select driversexceed a predetermined pulse width, a gate is activated to actuate analarm and to cut-off the supply voltage to pre vent the abnormal signalfrom damaging the memory elements.

BRIEF DESCRIPTION OF THE DRAWINGS Various objects, features andattendant advantages of the present invention will be more fullyappreciated as the same becomes better understood from the followingdetailed description of the present invention when considered inconnection with the accompanying drawings, in which:

FIG. 1 illustrates well-known examples of prior art semiconductor memoryelements;

FIG. 2 is a block diagram illustrating a semiconductor memory apparatus;

FIG. 3 shows the characteristic curves of the operation of the apparatusof FIG. 2;

FIG. 4 is a schematic diagram illustrating a preferred embodiment of thepresent invention; and

FIGS. 5 and 6 are timing diagrams helpful in understanding the operationof the device of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings,wherein like reference numerals designate identical or correspondingparts throughout the several views, and more particularly to FIGv 4thereof a preferred embodiment of this invention is shown as comprisinga dynamic type MOS- RAM comprising a memory of 4K (4096) words X n bits.Numerals 31,, 3L 31 and 31 represent the address signal input terminal sthat ar e supplied with the decoded address signals 1K, 2K, 3K and 4?,respectively, for chip selecting. These address signal input terminals31,, 31 31 and 31 are connected to one input terminal of the NAND gates31, 32 32 and 32,, respectively. The other input terminal of said NANDgates are connectedin common, and are supplied with the refresh signalREF. The output terminals of NAND gates 32,, 32 32 and 32 are connectedto a first input terminal of PRE drivers 34,, 34 34 and 34,,respectively, in MOS driving circuits 33, 33 33,-, and 33,,respectively. The second input terminal of said PRE drivers areconnected in common and are supplied with precharge signal PRE. Thefirst input terminal of said PRE drivers 34,. 34 34;, and 34 areadditionally each connected to an input terminal of CS drivers 35,, 3535 and 35 respectively. The other input terminals of CS drivers 35,. 35-35 and 35 are connected in common, and are supplied with the chip selectsignal CS. The output terminals of each MOs driving circuit, consistingof the outputs of a PRE driver and a CS driver, are connected to aMOS-RAM. For example, the out put terminals of MOS driving circuit 31,,consisting of the outputs of PRE driver 34, and CS driver 35,, areconnected to MOS-RAM 36 MOS-RAM devices 36 36, 36 36 etc, are suppliedwith a read/write (R/W) signal and are connected to an input terminal ofsense amplifiers 37 37 37 The other input terminals of the senseamplifiers are connected in common, and are supplied with a sense strobesignal ST. Said driving circuits 33,, 33 32 and 33,, are also connectedto the protecting device of the present invention.

The protecting device of the present invention generally comprises apair of detecting signal invert circuits 42 and 42 and wave adjustingcircuits 49 49 49;, and 49 the operation of which will become more clearhereinafter. Diodes 4] 41 41 and 41 are connected to the outputterminals of CS drivers 35,, 35 35 and 35 respectively. The anodeelectrodes of said diodes are connected in common to the input terminal42 of the detecting signal invert circuit 42, which is connected to theanode electrode of the diode 43, and is supplied with a driving sourcevoltage +Vcc through the resistor 44. The cathode electrode of diode 43is connected to the base electrode of NPN transistor 46 through thediode 45, and is connected to ground through the resistor 47. Theemitter electrode of transister 46 is connected to ground through theresistor 48, and is also connected to the output terminal 42 Thecollector electrode of transistor 46 is connected to the driving sourcevoltage +Vcc. A low voltage signal is delivered at output terminal 42 ofdetecting sig nal invert circuit 42, if a negative signal is deliveredfrom each output terminal of the CS drivers 35 35 35 and 35,. Outputterminal 42 is connected to the input terminal 49 of the wave adjustingcircuit 49 which serves to shorten the pulse width of the low voltagesignal. The input terminal 49 of wave adjusting circuit 49, is connectedto the input terminal of the inverter 50. This inverters output terminalis connected to one input terminal of a NAND gate 51 and is connected tothe other input terminal through the delay circuit 52. The outputterminal 49 is connected to the input terminal 49 of another waveadjusting circuit 49 The output terminal 49 of wave adjusting circuit 49is connected to one input terminal of a NAND gate 53.

The output terminals of PRE drivers 34,, 34 34 and 34, are connected toa cathode electrode of diodes 54 S4 S4 and 54 respectively The anodeelectrodes of said diodes are connected in common to the input terminal42 of the other detecting signal invert circuit 42 The output terminal42 of detecting signal invert circuit 42 is connected to the inputterminal 49 of the wave adjusting circuit 49 and the output terminal 49is connected to the input terminal 49 of the wave adjusting circuit 49The output terminal 49 of wave adjusting circuit 49 is connected to theother input terminal of NAND gate 53. The output terminal of NAND gate53 is connected to the abnormal signal output terminal 55. This outputterminal 55 is connected to an alarm means 60 and/or a source voltagecut-off means 70, which are actuated in a manner to be describedhereinafter.

The operation of this mbodiment will be more fully understood with theaid FIGv 5 and FIG. 6. Decoded address signal TTL 0 lev is supplied tothe address sig nal input terminal 31 and a negative fir signal is supplied to NAND gate 32,. Therefore, the signal 1 is yielded at the outputterminal of NAND gate 32 This signal is supplied to the MOS drivingcircuit 33 If posi tive logic with the CS signal and the PRE signal isapproved, an MOS level signal is transmitted to one column of MOS-RAMdevices 36 36 36 The output signal from each device 36, 36 .36 are transmitted to sense amplifiers 37,, 37 37 These sig nals and the ST signalare logically summed, and the amplified signals are yielded from theoutput terminals of the sense amplifiers.

lfa normal negative pulse having a proper time duration is deliveredfrom CS driver 35 of the driving circuit 33 it is transmitted to theinput terminal 42, of the detecting signal invert circuit 42, throughthe diode 41 In detecting signal invert circuit 42 a driving voltage+Vcc is supplied to the base electrode of transistor 46 through resistor44 and diodes 43 and 45 during the condition when no pulse is suppliedto input terminal 42 Thus, at the output terminal 42 a low level voltage0 signal is yielded (shown in FIG. 5(a)). This 0 signal is supplied tothe input terminal 49, of wave adjusting circuit 49,, and becomes a lsignal after being reversed through the inverter 50 as shown in FIG.5(b). This l signal is supplied to one input terminal of NAND gate 51. Asimilar pulse, delayed by time td is delivered to the other inputterminal through delay circuit 52 as seen in FIG. 5(0). Thus, a reversedand shortened pulse is yielded at output terminal 49 of NAND gate SI asshown in FIG. 5(d). This delayed pulse is subsequently supplied to theinput terminal of wave adjusting circuit 49 and a reversed signal isyielded from the output terminal of the inverter 50, as shown in FIG.5(a). This signal is supplied to one input terminal of NAND gate 51, andis also supplied to delay circuit 52. Thus, a time td, delayed pulse issupplied to the other input terminal of NAND gate 51, as shown in FIG.5(f). Therefore, the output signal at the output terminal of NAND gate51 is not varied, as shown in FIG. 5(g), and maintains the I level. Thissignal is supplied to one input terminal of NAND gate 53. Similarly, theoutput signal from PRE driver 34 of the driving circuit 33 will besupplied to the other input terminal of NAND gate 53. Thus, a 0 signalappears at the abnormal signal output terminal 55 during normaloperating conditions, and alarm means 60 and source voltage cutoff meansconnected to output terminal 55 will not be acti vated.

If, however, an abnormal negative pulse having an undesirably long timeduration t is delivered from CS driver 35 of driving circuit 33 it willbe supplied to input terminal 42 of the detecting signal invert circuit42 through the diode 41 The transistor 46 cuts off, and a low level 0signal having a time width 1, will be delivered from output terminal 42,as shown in FIG. 6(a). This 0 level signal is supplied to the inputterminal 49 of wave adjusting circuit 49,, and becomes reversed to a 1level signal through inverter 50, as shown in FIG. 6(b). This signal issupplied to one input terminal of NAND gate 51. A time rd, delayed pulseis delivered to the other input terminal of NAND gate 51 through delaycircuit 52 as shown in FIG. 6(0). Therefore. the reversed pulse isyielded at the output terminal 49 of NAND gate 51, as shown in FIG.6(d). This shortened pulse is supplied to the input terminal of the waveadjusting circuit 49 and subsequently a reversed pulse is delivered atthe output terminal of the inverter 50, as shown in FIG. 6 (e). Thissignal is supplied to one input terminal of NAND gate 51, and is alsosupplied to the delay circuit 52, the delayed pulse therefrom, as seenin FIG. 6U), being supplied to the other input terminal of NAND gate 51.Thus, a reversed level pulse is delivered at the output terminal of NANDgate 51, as shown in H6. 6(g). This signal is supplied to one inputterminal of NAND gate 53. Therefore, a reversed l level signal isyielded from the output terminal of NAND gate 53, as shown in FIG. 6(h).This 1 level signal is delivered at the abnormal signal output terminal55, and an alarm device 60 or source voltage cut-off device 70, eachconnected to said terminal 55, are thereby actuated.

By virtue of the aforedescribed embodiment of the present invention,trouble in the driving circuits can be effectively detected in a simplemanner to protect the memory elements from serious damage.

Obviously. numerous modifications and variations of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims theinvention may be practiced otherwise than as specifically describedherein.

What is claimed as new and desired to be secured by Letters Patent ofthe United States is:

1. Apparatus for protecting the semi-conductor memory elements in asemiconductor device from damage due to abnormal pulses from the drivingcircuitry thereof, which comprises:

means for sampling a pulse signal from said driving circuitry;

means for time-delaying said pulse signal;

means for comparing said pulse signal with said timedelayed pulse signaland for issuing an output signal indicative of whether said pulse signalexceeds a pre-determined pulse width;

said time-delaying and comparing means comprising a first inverterhaving an input and an output for receiving as its input the pulsesignal from said driving circuitry;

a second inverter having an input and an output;

a first delay circuit having an input and an output;

a second delay circuit having an input and an output;

a first NAND gate having two inputs and an output;

a second NAND gate having two inputs and an out- P means connecting theoutput of the first inverter to the input of the first delay circuit andto an input of the first NAND gate; means connecting the output of thefirst delay circuit to the other input of the first NAND gate;

means connecting the output of the first NAND gate to the input of thesecond inverter;

means connecting the output of the second inverter to the input of thesecond delay circuit and to an input of the second NAND gate;

means connecting the output of the second delay circuit to the otherinput of the second NAND gate;

the output of the second NAND gate being indicative of whether saidpulse signal exceeds a predetermined pulse width.

2. Apparatus for protecting the semiconductor memory elements in asemiconductor memory device from damage due to abnormal pulses from aprecharge signal driver and/or a chip select signal driver, whichcomprises:

first and second diode means for sampling a pulse signal from saidprecharge signal driver and said chip select signal driver.respectively;

first and second means connected to receive the output signals from saidfirst and second sampling means, respectively. for establishingrespective voltage signals indicative of the presence or ab sence ofsaid output signals;

first and second wave-adjusting means connected to receive said voltagesignals from said first and second establishing means, respectively,said first and second wave-adjusting means including means fortime-delaying said voltage signals, gating means for comparing saidvoltage signals with said time delayed voltage signals and for issuingfirst and second difference signals indicative of whether said voltagesignals exceed a predetermined pulse width, means for time-delaying saidfirst and second difference signals, gating means for comparing saidfirst and second difference signals with said time-delayed first andsecond difference signals and for issuing third and fourth differencesignals indicative of whether said first and second difference signalsexceed a predetermined pulse width; and

sensing means for receiving as its inputs the outputs of said first andsecond wave-adjusting means and for issuing an output signal responsiveto said inputs.

3. The apparatus according to claim 2 wherein said sensing meanscomprises a NAND gate, the output of which is connected to alarm meansand source voltage cut-off means.

1. Apparatus for protecting the semi-conductor memory elements in asemiconductor device from damage due to abnormal pulses from the drivingcircuitry thereof, which comprises: means for sampling a pulse signalfrom said driving circuitry; means for time-delaying said pulse signal;means for comparing said pulse signal with said time-delayed pulsesignal and for issuing an output signal indicative of whether said pulsesignal exceeds a pre-determined pulse width; said time-delaying andcomparing means comprising a first inverter having an input and anoutput for receiving as its input the pulse signal from said drivingcircuitry; a second inverter having an input and an output; a firstdelay circuit having an input and an output; a second delay circuithaving an input and an output; a first NAND gate having two inputs andan output; a second NAND gate having two inputs and an output; meansconnecting the output of the first inverter to the input of the firstdelay circuit and to an input of the first NAND gate; means connectingthe output of the first delay circuit to the other input of the firstNAND gate; means connecting the output of the first NAND gate to theinput of the second inverter; means connecting the output of the secondinverter to the input of the second delay circuit and to an input of thesecond NAND gate; means connecting the output of the second delaycircuit to the other input of the second NAND gate; the output of thesecond NAND gate being indicative of whether said pulse signal exceeds apredetermined pulse width.
 2. Apparatus for protecting the semiconductormemory elements in a semiconductor memory device from damage due toabnormal pulses from a precharge signal driver and/or a chip selectsignal driver, which comprises: first and second diode means forsampling a pulse signal from said precharge signal driver and said chipselect signal driver, respectively; first and second means connected toreceive the output signals from said first and second sampling means,respectively, for establishing respective voltage signals indicative ofthe presence or absence of said output signals; first and secondwave-adjusting means connected to receive said voltage signals from saidfirst and second establishing means, respectively, said first and secondwave-adjusting means including means for time-delaying said voltagesignals, gating means for comparing said voltage signals with said timedelayed voltage signals and for issuing first and second differencesignals indicative of whether said voltage signals exceed apredetermined pulse width, means for time-delaying said first and seconddifference signals, gating means for comparing said first and seconddifference signals with said time-delayed first and second differencesignals and for issuing third and fourth difference signals indicativeof whether said first and second difference signals exceed apredetermined pulse width; and sensing means for receiving as its inputsthe outputs of said first and second wave-adjusting means and forissuing an output signal responsive to said inputs.
 3. The apparatusaccording to claim 2 wherein said sensing means comprises a NAND gate,the output of which is connected to alarm means and source voltagecut-off means.